
24
LTC2424/LTC2428
APPLICATIONS INFORMATION
WUU
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A similar situation may occur during the sleep state when
CSADC is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH
(within the time period defined above as t
EOCtest
), the
internal pull-up is activated. For a heavy capacitive load
on the SCK pin, the internal pull-up may not be adequate
to return SCK to a HIGH level before CSADC goes LOW
again. This is not a concern under normal conditions
where CSADC remains LOW after detecting EOC = 0. This
situation is easily avoided by adding an external 10k pull-
up resistor to the SCK pin.
DIGITAL SIGNAL LEVELS
The LTC2424/LTC2428’s digital interface is easy to use.
Its digital inputs (F
O
, CSADC, CSMUX, CLK, D
IN
and SCK
in External SCK mode of operation) accept standard
TTL/CMOS logic levels and can tolerate edge rates as slow
as 100µs. However, some considerations are required to
take advantage of exceptional accuracy and low supply
current.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the accuracy of the LTC2424/LTC2428,
it is very important to minimize the ground path imped-
ance which may appear in series with the input and/or
reference signal and to reduce the current which may flow
through this path. The ZS
SET
pin (Pin 5) should be con-
nected directly to the signal ground.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.
Figure 17. Internal Serial Clock with Reduced Data Output Length Timing Diagram
SCKCLK
SDO
D
IN
CSADC
CSMUX
t
EOCtest
MSB
EXRSIG
BIT8BIT12 BIT11 BIT10 BIT9BIT19BIT18BIT20BIT21BIT22BIT23
24248 F17
TEST EOC
DON’T CARE DON’T CAREEN D2 D1 D0
Hi-Z Hi-ZHi-Z
TEST EOC TEST EOC
V
CC
CS
10k
F
O
FS
SET
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
GND
D
IN
ZS
SET
SDO
0.1V
TO V
CC
CH0
TO CH7
–0.12V
REF
TO 1.12V
REF
2.7V TO 5.5V
LTC2424/LTC2428
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
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